library ieee;
use ieee.std_logic_1164.all;
--器件T1：组合逻辑器件，
--用于产生ALU的进位输入Cin即alu_cin，受两位控制信号SCI的选择控制，
--输入为标志寄存的输出FLAG_C
entity t1 is
	port(flag_c:in std_logic;
	     sci:in std_logic_vector(1 downto 0);	--控制信号
	     alu_cin:out std_logic);
end t1;

architecture behave of t1 is
begin
	process(sci,flag_c)
	begin
		case sci is
		when "00"=>
		alu_cin<='0';
		when "01"=>
		alu_cin<='1';
		when "10"=>
		alu_cin<=flag_c;
		when others=>
		alu_cin<='0';
		end case;
	end process;
end behave;